| 書目名稱 | Mismatch and Noise in Modern IC Processes | | 編輯 | Andrew Marshall | | 視頻video | http://file.papertrans.cn/635/634769/634769.mp4 | | 叢書名稱 | Synthesis Lectures on Digital Circuits & Systems | | 圖書封面 |  | | 描述 | Component variability, mismatch, and various noise effects are major contributors to design limitations in most modern IC processes. Mismatch and Noise in Modern IC Processes examines these related effects and how they affect the building block circuits of modern integrated circuits, from the perspective of a circuit designer.Variability usually refers to a large scale variation that can occur on a wafer to wafer and lot to lot basis, and over long distances on a wafer. This phenomenon is well understood and the effects of variability are included in most integrated circuit design with the use of corner or statistical component models. Mismatch, which is the emphasis of section I of the book, is a local level of variability that leaves the characteristics of adjacent transistors unmatched. This is of particular concern in certain analog and memory systems, but also has an effect on digital logic schemes, where uncertainty is introduced into delay times, which can reduce margins and introduce ‘race‘ conditions. Noise is a dynamic effect that causes a local mismatch or variability that can vary during operation of a circuit, and is considered in section II. Noise can be the result of | | 出版日期 | Book 2009 | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-031-79791-0 | | isbn_softcover | 978-3-031-79790-3 | | isbn_ebook | 978-3-031-79791-0Series ISSN 1932-3166 Series E-ISSN 1932-3174 | | issn_series | 1932-3166 | | copyright | Springer Nature Switzerland AG 2009 |
The information of publication is updating
|
|
|Archiver|手機版|小黑屋|
派博傳思國際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-14 23:41
發(fā)表于 2025-3-21 18:05:42
