Titlebook: Microelectronic Test Structures for CMOS Technology; Manjul Bhushan,Mark B. Ketchen Book 2011 Springer Science+Business Media, LLC 2011 Bh

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Flinch

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Test Structures for SOI Technology,e circuits have higher immunity to latch up and to soft errors generated by incident radiation. In partially depleted silicon-on-insulator (PD-SOI) technology, electrical isolation of the MOSFET body from the underlying silicon substrate facilitates modulation of the threshold voltage, providing an opportunity for further circuit performance gain.

Peristalsis

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Measured

Capacitors, of inter-level dielectric properties such as effective dielectric constant and film geometries such as layer thicknesses and linewidths. . characteristics of diodes are used for profiling carrier densities in silicon devices. Carrier lifetime measurement in silicon utilizes . and . characteristics of MOS capacitors.

Solace

MOSFETs,Statistical fluctuations in the number of dopant atoms in the channel and local linewidth variations lead to variability in parameters of nominally identical MOSFETs. Hence, the focus on MOSFET macro design and test in this chapter primarily concerns DC . and variability characterization.

Dungeon

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