書目名稱 | Memory Controllers for Mixed-Time-Criticality Systems |
副標(biāo)題 | Architectures, Metho |
編輯 | Sven Goossens,Karthik Chandrasekar,Kees Goossens |
視頻video | http://file.papertrans.cn/631/630463/630463.mp4 |
概述 | Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify.Explains the concepts of predictability and composability and how they address the design and v |
叢書名稱 | Embedded Systems |
圖書封面 |  |
描述 | .This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.. |
出版日期 | Book 2016 |
關(guān)鍵詞 | Memory Controllers; Memory Systems; Memory Controllers for Real-Time Embedded Systems; mixed-time-criti |
版次 | 1 |
doi | https://doi.org/10.1007/978-3-319-32094-6 |
isbn_softcover | 978-3-319-81196-3 |
isbn_ebook | 978-3-319-32094-6Series ISSN 2193-0155 Series E-ISSN 2193-0163 |
issn_series | 2193-0155 |
copyright | Springer International Publishing Switzerland 2016 |