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Titlebook: Low-Power Variation-Tolerant Design in Nanometer Silicon; Swarup Bhunia,Saibal Mukhopadhyay Book 2011 Springer Science+Business Media, LLC

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發(fā)表于 2025-3-21 19:01:28 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱(chēng)Low-Power Variation-Tolerant Design in Nanometer Silicon
編輯Swarup Bhunia,Saibal Mukhopadhyay
視頻videohttp://file.papertrans.cn/589/588899/588899.mp4
概述Presents important challenges in nanometer scale integrated circuit design.Presents a holistic view of Low-Power Variation-Tolerant Design.Covers modeling, analysis and design methodology for low powe
圖書(shū)封面Titlebook: Low-Power Variation-Tolerant Design in Nanometer Silicon;  Swarup Bhunia,Saibal Mukhopadhyay Book 2011 Springer Science+Business Media, LLC
描述Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
出版日期Book 2011
關(guān)鍵詞DFM; Design for Manufacturing; EDA; Electronic Design Automation; Integrated Circuit Design; Low Power IC
版次1
doihttps://doi.org/10.1007/978-1-4419-7418-1
isbn_softcover978-1-4899-8157-8
isbn_ebook978-1-4419-7418-1
copyrightSpringer Science+Business Media, LLC 2011
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沙發(fā)
發(fā)表于 2025-3-21 23:04:22 | 只看該作者
Power Dissipationd. This chapter covers the basics of the IC power consumption issue. It first investigates the sources of IC power dissipation, and then discusses recent techniques for IC power analysis. Finally, it studies recently proposed power optimization techniques from circuit and physical design to system synthesis.
板凳
發(fā)表于 2025-3-22 03:26:20 | 只看該作者
Low-Power and Variation-Tolerant Application-Specific System Designas power and performance with system level metrics such as quality-of-results and tolerance to variations (yield). The techniques presented in this chapter target various types of designs that include logic and memory architectures and complete DSP systems.
地板
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Book 2011c and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
7#
發(fā)表于 2025-3-22 17:06:45 | 只看該作者
Statistical Design of Integrated Circuitsst-silicon stage, we then present how a set of compact sensors may be used to predict the delay of a manufactured part, with known confidence, through a small set of measurements on the sensors: such data can then be used to drive adaptive post-silicon tuning approaches that are individualized to each manufactured part.
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發(fā)表于 2025-3-23 01:14:23 | 只看該作者
Low-Power and Variation-Tolerant Memory Designit techniques, post silicon adaptive repair techniques, and variation-tolerant SRAM peripherals. A self-repairing SRAM is discussed which adaptively adjusts its body bias to improve its reliability. Finally, a discussion on adaptive low-power and variation-tolerant SRAM design for multi-media applications is provided.
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發(fā)表于 2025-3-23 04:18:43 | 只看該作者
Variation and Aging Tolerance in FPGAs the ability to spread wear effects over the chip which is not possible in ASICs. This chapter examines the impact of variation and wear on FPGAs and notes the benefit that can be gained from variation and aging tolerance techniques that operate open-loop.
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發(fā)表于 2025-3-23 06:25:18 | 只看該作者
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