| 書目名稱 | Low-Power Design and Power-Aware Verification | | 編輯 | Progyna Khondkar | | 視頻video | http://file.papertrans.cn/589/588890/588890.mp4 | | 概述 | Complete Low-power design and verification engineering reference book – Required by a wide range of audience – verification engineer, design engineer, engineering policy maker, EDA tool developer, aca | | 圖書封面 |  | | 描述 | .Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base..LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF). Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination..The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r.egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of de | | 出版日期 | Book 2018 | | 關(guān)鍵詞 | Silicon Engineering; Low Power Design; Power Aware Verification; Unified Power Format (UPF); Static Veri | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-319-66619-8 | | isbn_softcover | 978-3-319-88286-4 | | isbn_ebook | 978-3-319-66619-8 | | copyright | Springer International Publishing AG 2018 |
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