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Titlebook: Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET; Nabil Shovon Ashraf Book 2018 Springer Nature Switzerland AG 2018

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發(fā)表于 2025-3-21 17:34:03 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET
編輯Nabil Shovon Ashraf
視頻videohttp://file.papertrans.cn/589/588815/588815.mp4
叢書名稱Synthesis Lectures on Emerging Engineering Technologies
圖書封面Titlebook: Low Substrate Temperature Modeling Outlook of Scaled n-MOSFET;  Nabil Shovon Ashraf Book 2018 Springer Nature Switzerland AG 2018
描述Low substrate/lattice temperature (< 300 K) operation of n-MOSFET has been effectively studied by device research and integration professionals in CMOS logic and analog products from the early 1970s. The author of this book previously composed an e-book in this area where he and his co-authors performed original simulation and modeling work on MOSFET threshold voltage and demonstrated that through efficient manipulation of threshold voltage values at lower substrate temperatures, superior degrees of reduction of subthreshold and off-state leakage current can be implemented in high-density logic and microprocessor chips fabricated in a silicon die. In this book, the author explores other device parameters such as channel inversion carrier mobility and its characteristic evolution as temperature on the die varies from 100-300 K. Channel mobility affects both on-state drain current and subthreshold drain current and both drain current behaviors at lower temperatures have been modeled accurately and simulated for a 1 ??m channel length n-MOSFET. In addition, subthreshold slope which is an indicator of how speedily the device drain current can be switched between near off current and ma
出版日期Book 2018
版次1
doihttps://doi.org/10.1007/978-3-031-02034-6
isbn_softcover978-3-031-00906-8
isbn_ebook978-3-031-02034-6Series ISSN 2381-1412 Series E-ISSN 2381-1439
issn_series 2381-1412
copyrightSpringer Nature Switzerland AG 2018
The information of publication is updating

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978-3-031-00906-8Springer Nature Switzerland AG 2018
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Introduction,tnessed a plateau at this node where industry and institutional research professionals are hesitant to forecast what future architecture will assume once the feature size of a transistor enters 7 nm and below. In a previous book [1], also written by the current author, it has been brought to the att
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Historical Perspectives of Scaled MOSFET Evolution,loyments such as stress and strain and wafer orientations. At present, all these adapted incentives to device architectures are performed at 300 K as, although evidence is now on hand about additional performance improvements at temperatures around 77 K, the apparent prohibition to alter substrate t
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