Titlebook: Low Power Methodology Manual; For System-on-Chip D Michael Keating,David Flynn,Kaijian Shi Book 2007 Springer-Verlag US 2007 Aitken.Keating

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FIN

Integrated Circuits and Systemshttp://image.papertrans.cn/l/image/588800.jpg

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有法律效應

Multi-Voltage Design,The techniques discussed in the previous chapter are mature; engineers have been using them for some time, and design tools have supported them for years. With this chapter, we begin discussing more recent and aggressive approaches to reducing power: power gating and adaptive voltage scaling.

機警

Power Gating Overview,Leakage power dissipation grows with every generation of CMOS process technology. This leakage power is not only a serious challenge to battery powered or portable products but increasingly an issue that has to be addressed in tethered equipment such as servers, routers, and set-top boxes.

貨物

Designing Power Gating,This chapter describes power gating design from a front-end, RTL perspective. Figure 5-1 shows the critical components of such a design.

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承認

A Power Gating Example,The SALT technology demonstrator project provided a platform for testing the approaches to power gating and state retention described in this book. In this chapter we give some more details on the system design and RTL coding for this project.

DUST

Frequency and Voltage Scaling Design,Scaling the supply voltage of CMOS is possible over a technology-specific range; gate delays, setup and hold times and even memory access times scale monotonically with reduced operating voltage over a limited range. Linear voltage reduction results in a square-law reduction in both dynamic power consumption and in leakage power.