| 書目名稱 | Low Power Digital CMOS Design | | 編輯 | Anantha P. Chandrakasan,Robert W. Brodersen | | 視頻video | http://file.papertrans.cn/589/588797/588797.mp4 | | 圖書封面 |  | | 描述 | Power consumption has become a major design consideration forbattery-operated, portable systems as well as high-performance,desktop systems. Strict limitations on power dissipation must be metby the designer while still meeting ever higher computationalrequirements. A comprehensive approach is thus required at all levelsof system design, ranging from algorithms and architectures to thelogic styles and the underlying technology. .Potentially one of the most important techniques involves combiningarchitecture optimization with voltage scaling, allowing a trade-offbetween silicon area and low-power operation. Architecturaloptimization enables supply voltages of the order of 1 V usingstandard CMOS technology. Several techniques can also be used tominimize the switched capacitance, including representation,optimizing signal correlations, minimizing spurious transitions,optimizing sequencing of operations, activity-driven power down, etc.The high- efficiency of DC-DC converter circuitry required forefficient, low-voltage and low-current level operation is described byStratakos, Sullivan and Sanders. The application of various low-powertechniques to a chip set for multimedia applications | | 出版日期 | Book 1995 | | 關鍵詞 | CMOS; Potential; Signal; Standard; computer; logic; microprocessor; multimedia | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-2325-3 | | isbn_softcover | 978-1-4613-5984-5 | | isbn_ebook | 978-1-4615-2325-3 | | copyright | Springer Science+Business Media New York 1995 |
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