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Titlebook: Low Power Design in Deep Submicron Electronics; Wolfgang Nebel,Jean Mermet (Directeur de recherche Book 1997 Kluwer Academic Publishers 19

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發(fā)表于 2025-3-21 19:02:20 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱Low Power Design in Deep Submicron Electronics
編輯Wolfgang Nebel,Jean Mermet (Directeur de recherche
視頻videohttp://file.papertrans.cn/589/588795/588795.mp4
叢書名稱Nato ASI Subseries E:
圖書封面Titlebook: Low Power Design in Deep Submicron Electronics;  Wolfgang Nebel,Jean Mermet (Directeur de recherche Book 1997 Kluwer Academic Publishers 19
描述.Low Power Design in Deep Submicron Electronics. deals withthe different aspects of low power design for deep submicronelectronics at all levels of abstraction from system level to circuitlevel and technology. Its objective is to guide industrial andacademic engineers and researchers in the selection of methods,technologies and tools and to provide a baseline for furtherdevelopments. Furthermore the book has been written to serve as atextbook for postgraduate student courses. In order to achieve bothgoals, it is structured into different chapters each of whichaddresses a different phase of the design, a particular level ofabstraction, a unique design style or technology. These design-relatedchapters are amended by motivations in Chapter 2, which presentsvisions both of future low power applications and technologyadvancements, and by some advanced case studies in Chapter 9. ..From the Foreword:. .`... This global nature of design for low power was well understood byWolfgang Nebel and Jean Mermet when organizing the NATO workshop whichis the origin of the book. They invited the best experts in the fieldto cover all aspects of low power design. As a result the chapters inthis book are
出版日期Book 1997
關(guān)鍵詞Analysis; CMOS; algorithms; computer-aided design (CAD); electronics; integrated circuit; layout; logic; mic
版次1
doihttps://doi.org/10.1007/978-1-4615-5685-5
isbn_softcover978-0-7923-8103-7
isbn_ebook978-1-4615-5685-5
copyrightKluwer Academic Publishers 1997
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Application and Technology Forecastrcuits have been made steadily larger, incorporating more and more functions on each chip, until now it is essentially possible to put an entire mainframe computer on a single piece of silicon, excluding perhaps the memory. This progress has steadily created new applications for electronics, and in
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Combinational Circuit Optimization (see Figure 1). Power optimization techniques at the system, architectural (behavioral) design level, register-transfer (RT) level, physical design level, and the circuit level have been addressed by researchers in the past. Logic synthesis however, is an important part of the design cycle for a di
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RT and Algorithmic-Level Optimization for Low Powerhigh-level synthesis, a solid characterization of the various issues that must be addressed during this design phase has not yet been established. As a consequence, essential decisions on the specific optimization strategy to be followed are usually taken based on previous experience.
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