| 書目名稱 | Loop Tiling for Parallelism | | 編輯 | Jingling Xue | | 視頻video | http://file.papertrans.cn/589/588637/588637.mp4 | | 叢書名稱 | The Springer International Series in Engineering and Computer Science | | 圖書封面 |  | | 描述 | Loop tiling, as one of the most important compileroptimizations, is beneficial for both parallel machines anduniprocessors with a memory hierarchy. This book explores the use ofloop tiling for reducing communication cost and improving parallelismfor distributed memory machines. The author provides mathematicalfoundations, investigates loop permutability in the framework ofnonsingular loop transformations, discusses the necessary machineriesrequired, and presents state-of-the-art results for findingcommunication- and time-minimal tiling choices. Throughout the book,theorems and algorithms are illustrated with numerous examples anddiagrams. The techniques presented in .Loop Tiling forParallelism. can be adapted to work for a cluster of workstations,and are also directly applicable to shared-memory machines once themachines are modeled as BSP (Bulk Synchronous Parallel) machines..Features and key topics: . . Detailed review of themathematical foundations, including convex polyhedra and cones; ..Self-contained treatment of nonsingular loop transformations, codegeneration, and full loop permutability; .. Tiling loop nests byrectangles and parallelepipeds, including their mathematicaldef | | 出版日期 | Book 2000 | | 關(guān)鍵詞 | algorithms; compiler; distributed memory; optimization; processor | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-4337-4 | | isbn_softcover | 978-1-4613-6948-6 | | isbn_ebook | 978-1-4615-4337-4Series ISSN 0893-3405 | | issn_series | 0893-3405 | | copyright | Springer Science+Business Media New York 2000 |
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