| 書目名稱 | Logic Minimization Algorithms for VLSI Synthesis |
| 編輯 | Robert K. Brayton,Gary D. Hachtel,Alberto L. Sangi |
| 視頻video | http://file.papertrans.cn/588/587878/587878.mp4 |
| 叢書名稱 | The Springer International Series in Engineering and Computer Science |
| 圖書封面 |  |
| 描述 | The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor- tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza- tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen- tation was created in the |
| 出版日期 | Book 1984 |
| 關(guān)鍵詞 | Maxima; Phase; Potential; VLSI; algebra; algorithms; calculus; design; history; integrated circuit; logic; orga |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4613-2821-6 |
| isbn_softcover | 978-1-4612-9784-0 |
| isbn_ebook | 978-1-4613-2821-6Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Kluwer Academic Publishers 1984 |
|Archiver|手機(jī)版|小黑屋|
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