| 書目名稱 | Leakage in Nanometer CMOS Technologies | | 編輯 | Siva G. Narendra,Anantha Chandrakasan | | 視頻video | http://file.papertrans.cn/583/582468/582468.mp4 | | 概述 | Each chapter is written by a different combination of experts on the subjects.Includes supplementary material: | | 叢書名稱 | Integrated Circuits and Systems | | 圖書封面 |  | | 描述 | Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation technique | | 出版日期 | Book 2006 | | 關(guān)鍵詞 | CMOS; architecture; microprocessor; testing; transistor | | 版次 | 1 | | doi | https://doi.org/10.1007/0-387-28133-9 | | isbn_softcover | 978-1-4419-3826-8 | | isbn_ebook | 978-0-387-28133-9Series ISSN 1558-9412 Series E-ISSN 1558-9420 | | issn_series | 1558-9412 | | copyright | Springer-Verlag US 2006 |
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