Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation; 22nd International W José L. Ayala,Delong Sha

新石器時(shí)代

書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影響因子(影響力)




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影響因子(影響力)學(xué)科排名




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation網(wǎng)絡(luò)公開(kāi)度




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation網(wǎng)絡(luò)公開(kāi)度學(xué)科排名




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引頻次




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引頻次學(xué)科排名




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用學(xué)科排名




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation讀者反饋




書(shū)目名稱(chēng)Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation讀者反饋學(xué)科排名

Chemotherapy

Pedagogy

Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths,t, only statistical information of the input-stream is needed. The errors of the estimated Hamming and signal distance properties are in the range of 5% to 14% The result of an estimation is available nearly instantaneously since look-up tables are used for implementation.

燈絲

Direct Statistical Simulation of Timing Properties in Sequential Circuits,is is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45nm CMOS technology.

Ischemic-Stroke

NAVEN

An Extended Metastability Simulation Method for Synchronizer Characterization,on simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose an extended simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state-of-the-art simulation methods and with measurements of a 65nm LP CMOS test-chip.

無(wú)孔

發(fā)芽

Adaptive Synchronization for DVFS Applications,ncy by evaluating flip-flop synchronization performance dynamically. The proposed design meets a reliability criterion without relying on excessively-conservative synchronizers to accommodate for worst-case performance.

Panacea

Muller C-Element Metastability Containment,ult tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.

Intervention