Titlebook: IDDQ Testing of VLSI Circuits; Ravi K. Gulati,Charles F. Hawkins Book 1993 Springer Science+Business Media New York 1993 CMOS.VLSI.complex

連接

Quiescent Current Analysis and Experimentation of Defective CMOS Circuits,e 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on .. has been investigated by electrical simulation and experimentation.

Mere僅僅

Generation and Evaluation of Current and Logic Tests for Switch-Level Sequential Circuits,rithm for generating current and logic tests is introduced. Clear definitions for analyzing the effectiveness of the joint test generation approach are derived. Experimental results are presented for demonstrating high coverage of stuck-at, stuck-on, and stuck-open faults for switch level circuits when both current and logic tests are used.

技術(shù)

Proportional BIC Sensor for Current Testing,portional to i. Additional features are the possibility of continuous measure of i. and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.

Brittle

jaundiced

Reliability Benefits of ,,,al CMOS technology, the user obtains a product with greater reliability. The data presented within this article, along with increasing customer focus on zero defects, clearly support I. implementation.

pineal-gland

沙漠

abolish

使厭惡

978-1-4613-6377-4Springer Science+Business Media New York 1993

享樂(lè)主義者

https://doi.org/10.1007/978-1-4615-3146-3CMOS; VLSI; complexity; computer-aided design (CAD); integrated circuit; logic; metal-oxide-semiconductor