Titlebook: ICIPEG 2016; Proceedings of the I Mariyamni Awang,Berihun Mamo Negash,Abdul Ghani Md Conference proceedings 2017 Springer Nature Singapore

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Shahram Danaei,Deva Ghoshplores the concept of hybrid CMOS-nano circuit design for leveraging the best of scaled CMOS alongside of the best of novel nanoelectronics. This is accomplished by describing some novel nanoelectronic devices and comparing them to the traditional MOSFET. After some discussion about circuit level co

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Hamed Hematpur,Syed Mohammad Mahmood,Saeed Akbari,Negar Hadian Nasrole pairs to upset the storage nodes of SRAM cells. Such an upset is called a .. While such an upset can cause a data error, the device structures are not permanently damaged. If the voltage disturbance on a storage node of an SRAM cell is smaller than the noise margin of that node, the cell will co

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Ishaq Ahamad,Mariyamni Awang,Mudasser Mumtaz attempt to optimize the performance/cost ratio of such chips, designers are faced with a dilemma. Large arrays of fast SRAM help to boost the system performance. However, the area impact of incorporating large SRAM arrays into a chip directly translates into a higher chip cost. Balancing these requ

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