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Titlebook: How Transistor Area Shrank by 1 Million Fold; Howard Tigelaar Book 2020 Springer Nature Switzerland AG 2020 History of Transistor Scaling.

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發(fā)表于 2025-3-21 19:16:19 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱How Transistor Area Shrank by 1 Million Fold
編輯Howard Tigelaar
視頻videohttp://file.papertrans.cn/429/428713/428713.mp4
概述Written from a process integration point of view, in language accessible to a wide variety of readers.Provides readers with an understanding of how transistors work, how they are built, and the equipm
圖書封面Titlebook: How Transistor Area Shrank by 1 Million Fold;  Howard Tigelaar Book 2020 Springer Nature Switzerland AG 2020 History of Transistor Scaling.
描述.?This book explains in layman’s terms how CMOS transistors work. ?The author explains step-by-step how CMOS transistors are built, along with an explanation of the purpose of each process step. He describes for readers the key inventions and developments in science and engineering that overcame huge obstacles, enabling engineers to shrink transistor area by over 1 million fold and build billions of transistor switches that switch over a billion times a second, all on a piece of silicon smaller than a thumbnail..
出版日期Book 2020
關(guān)鍵詞History of Transistor Scaling; Moore’s Law; Semiconductors and Insulators Scaling; Lithography Chemistr
版次1
doihttps://doi.org/10.1007/978-3-030-40021-7
isbn_softcover978-3-030-40023-1
isbn_ebook978-3-030-40021-7
copyrightSpringer Nature Switzerland AG 2020
The information of publication is updating

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Overview of Integrated Circuit Manufacturing,Section . is an overview of how integrated circuits are manufactured. Section . describes some of the more commonly used transistors found in ICs. Section . describes how integrated circuits are packaged and provides examples of IC packages.
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發(fā)表于 2025-3-22 05:46:29 | 只看該作者
Engineering MOS Transistors for High Speed and Low Power,Explained are the sources of resistance and capacitance in an MOS transistor and how they impact MOS transistor speed and power. Trade-offs when simultaneously engineering MOS transistors for high speed and low power are discussed.
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發(fā)表于 2025-3-22 10:19:30 | 只看該作者
CMOS Inverter Manufacturing Flow: Part 3 Additional Levels of Metal Through PO,Advanced ICs may require up to a dozen or move levels of wiring to accommodate the billions of transistors. This chapter presents how additional wiring layers are added and discusses some of the associated engineering challenges.
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發(fā)表于 2025-3-22 15:35:43 | 只看該作者
The Incredible Shrinking IC: Part 2 FEOL Isolation Scaling and Transistor Scaling,This chapter presents histories and key inventions as transistors and the isolation between transistors scaled 1000-fold.
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