Titlebook: Higher-Level Hardware Synthesis; Richard Sharp Book 2004 Springer-Verlag Berlin Heidelberg 2004 Hardware.SAFL.VHDL.VLSI specifications.Ver

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4. Soft SchedulingWe have seen that the SAFL language facilitates the description of hardware as a set of interconnected resources. These resources run concurrently and may be shared. The interaction between parallelism and resource-sharing leads to an obvious problem: how does one ensure that shared resources are accessed mutually exclusively?

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5. High-Level Synthesis of SAFLIn order to justify our claim that ”the SAFL language is suitable for hardware description and synthesis” a high-level synthesis tool for SAFL has been designed and implemented. We refer to our HLS tool for SAFL as ..

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6. Analysis and Optimisation of Intermediate CodeIn this chapter we give examples of the kinds of analyses and optimisations which can be applied to the FLaSH compiler’s intermediate graphs. The analyses and optimisations presented here have been implemented as part of the FLaSH compiler.

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10. Case StudyThe purpose of this chapter is give an overview of the tools we use to translate SAFL(+) to silicon (see Section 10.1) with reference to a realistic example. A DES encryption/decryption circuit is specified in SAFL and implemented on an Altera Apex-II FPGA; area-time performance figures are given (Section 10.2).

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