Titlebook: High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip; Zheng Wang,Anupam Chattopadhyay Book 2018 Springe

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書目名稱High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip讀者反饋




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ANNUL

Arboreal

2367-3478 o presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.?.978-981-10-9321-0978-981-10-1073-6Series ISSN 2367-3478 Series E-ISSN 2367-3486

違法事實(shí)

Architectural Reliability Exploration,he feature of unequal error protection based on information criticality. In Sect.?. error confinement technique is proposed to correct errors in memory with statistical data, which reaches similar protection level with faster performance and less power consumption than traditional techniques.

壯觀的游行

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傲慢人

Zheng Wang,Anupam ChattopadhyayOffers a systematic approach to high-level reliability estimation and exploration.Presents step-by-step procedures for 11 novel techniques and solutions.Includes more than 100 figures and illustration

增強(qiáng)

針葉

Introduction,The last few decades have witnessed continuous scaling of CMOS technology, guided by Moore’s Law [136] (G.E. Moore, 38(8), 114 ff, 1965. IEEE Solid-State Circuits Newsl., 3(20), 33–35, 2006), to support devices with higher speed, less area, and less power.

加劇

Background,In this chapter, fundamental knowledge on reliability are discussed, including reliability definition, fault classification and fault models. In the next soft error and its evaluation metrics are elaborated, which is heavily used in the following chapters.