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Titlebook: High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications; Weitao Li,Fule Li,Zhihua Wang Book 2018 Springer

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發(fā)表于 2025-3-21 16:12:45 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications
編輯Weitao Li,Fule Li,Zhihua Wang
視頻videohttp://file.papertrans.cn/427/426740/426740.mp4
概述Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter.Presents three t
叢書名稱Analog Circuits and Signal Processing
圖書封面Titlebook: High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications;  Weitao Li,Fule Li,Zhihua Wang Book 2018 Springer
描述.This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference..Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter;.Presents three types of power-efficient architectures of the .high-resolution and high-speed AD converter;.Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance..
出版日期Book 2018
關鍵詞Analog to Digital Conversion; Digital to Analog Conversion; ADC; Power efficient AD converter; Low power
版次1
doihttps://doi.org/10.1007/978-3-319-62012-1
isbn_softcover978-3-319-87213-1
isbn_ebook978-3-319-62012-1Series ISSN 1872-082X Series E-ISSN 2197-1854
issn_series 1872-082X
copyrightSpringer International Publishing AG 2018
The information of publication is updating

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沙發(fā)
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板凳
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Reference Voltage Buffer,and high-resolution data conversion. In this chapter, we focus on the reference voltage buffer design. First, the traditional narrow-bandwidth buffer and wide-bandwidth buffer are depicted. The narrow-bandwidth one usually needs the large decoupling capacitors, which are difficult to be integrated o
地板
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發(fā)表于 2025-3-22 09:16:21 | 只看該作者
Comparator,curacy, but also in the speed of the data conversion. In this chapter, we discuss how to provide a comparator for a power-efficient and high-performance ADC. First, the circuit techniques that help to relax the requirements of the comparator are presented. Both the redundancy technique and the refer
6#
發(fā)表于 2025-3-22 15:45:40 | 只看該作者
Calibration,ow cost. In this chapter, we focus on the calibration techniques for the different ADC architectures. First, the error sources of the pipelined ADC, the SAR ADC, the flash ADC, and the time-interleaved ADC are presented. Second, an overview about the calibration principle is given. Then, we make a s
7#
發(fā)表于 2025-3-22 19:01:56 | 只看該作者
Design Case, and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improv
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978-3-319-87213-1Springer International Publishing AG 2018
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High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications978-3-319-62012-1Series ISSN 1872-082X Series E-ISSN 2197-1854
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