Titlebook: High-Performance Energy-Efficient Microprocessor Design; Vojin G. Oklobdzija,Ram K. Krishnamurthy Book 2006 Springer-Verlag US 2006 CMOS.C

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Static Memory Design,RAM cell. Subsequently, we discuss issues related to the design of memory peripherals such as voltage-mode and current-mode differential reads, single-ended reads, and control logic. We present design techniques to reduce SRAM dynamic and static power. We also cover issues pertaining to SRAM reliabi

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High-Performance Energy-Efficient Dual-Supply ALU Design, 64-bit mode with a 32-bit mode latency of 7 GHz (measured at 1.3V, 25° C). The lower- and upper-order 32-bit domains operate on separate off-chip supply voltages, enabling conditional turn-on/off of the 64-bit ALU mode operation and efficient power-performance optimization. High-speed single-rail d

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Binary Floating-Point Unit Design, a separate multiplier and adder. With one compound operation, effectively two dependent operations per cycle can be achieved. Even though a fused multiply-add dataflow is now common in today’s microprocessors, there are many details which have never been discussed in papers. This chapter shows the

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Processor Core and Low-Power SOC Design for Embedded Systems, 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches 1.8 MIPS/MHz, which is equivalent to the previous five-stage processor. The processor meets the requirements of a wide range of applications, and is suitable for digital a