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Titlebook: High-Level Verification; Methods and Tools fo Sudipta Kundu,Sorin Lerner,Rajesh K. Gupta Book 2011 Springer Science+Business Media, LLC 201

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發(fā)表于 2025-3-21 17:15:18 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱High-Level Verification
副標(biāo)題Methods and Tools fo
編輯Sudipta Kundu,Sorin Lerner,Rajesh K. Gupta
視頻videohttp://file.papertrans.cn/427/426629/426629.mp4
概述Offers industry practitioners already involved with high-level synthesis an invaluable reference to high-level verification.Uses a combination of formal techniques to do scalable verification of syste
圖書封面Titlebook: High-Level Verification; Methods and Tools fo Sudipta Kundu,Sorin Lerner,Rajesh K. Gupta Book 2011 Springer Science+Business Media, LLC 201
描述Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies upon advances in synthesis techniques as well as on incremental refinement of the design process. These refinements can be done manually or through elaboration tools. This book discusses verification of specific properties in designs written using high-level languages, as well as checking that the refined implementations are equivalent to their high-level specifications. The novelty of each of these techniques is that they use a combination of formal techniques to do scalable verification of sys
出版日期Book 2011
關(guān)鍵詞Design Automation; Design Validation; Design Verification; EDA; Embedded Systems; Equivalence Checking; He
版次1
doihttps://doi.org/10.1007/978-1-4419-9359-5
isbn_softcover978-1-4939-0101-2
isbn_ebook978-1-4419-9359-5
copyrightSpringer Science+Business Media, LLC 2011
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on of formal techniques to do scalable verification of systeGiven the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level
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Sudipta Kundu,Sorin Lerner,Rajesh K. Guptax motor-based actions in synchrony with other neural pathways and are recruited for the numerous complex cognitive and motor skills that develop as we progress toward adulthood. As such, we can expect that if one of these foundational networks is disrupted, its inclusion in the network configuration
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Malay K. Ganaialled internal and external experience, which alone — on no other grounds than prejudice — is commonly thought capable of effecting an original Objectification. The identity and, therefore, the objectivity of something ideal can be directly ‘seen’ (and, if we wished to give the word a suitable ampli
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Sudipta Kundu,Sorin Lerner,Rajesh K. Guptalecular profiling of cancer and aid in the diagnosis of cancer. The ability to detect diseased cells in biological fluids is important for early detection, monitoring disease progression or remission, and tracking drug efficacy. Our research has shown that aptamers can be used to purify cells from a
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