| 書目名稱 | High-Level Synthesis | | 副標(biāo)題 | from Algorithm to Di | | 編輯 | Philippe Coussy,Adam Morawiec | | 視頻video | http://file.papertrans.cn/427/426624/426624.mp4 | | 概述 | Extensive presentation of the leading research activities in HLS.Presentation of strengths of the available HLS technologies.User needs and application domains analysis.Overview of available EDA tool | | 圖書封面 |  | | 描述 | .The successful usage of Hardware Description Languages like VHDL and Verilog in design flows is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction. In the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow - a VHDL/Verilog RTL specification, followed by logical and physical synthesis - is indeed no more suitable. Thus, actual complex SoCs need new ESL level tools in order to raise the specification abstraction level up to the algorithmic / behavioral one. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools and approaches are required...The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious | | 出版日期 | Book 2008 | | 關(guān)鍵詞 | ASIC; Electronic Design Automation (EDA); Electronic System Level (ESL); FPGA; Field Programmable Gate A | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4020-8588-8 | | isbn_softcover | 978-90-481-7923-7 | | isbn_ebook | 978-1-4020-8588-8 | | copyright | Springer Science+Business Media B.V. 2008 |
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