| 書目名稱 | High-Level Power Analysis and Optimization | | 編輯 | Anand Raghunathan,Niraj K. Jha,Sujit Dey | | 視頻video | http://file.papertrans.cn/427/426623/426623.mp4 | | 圖書封面 |  | | 描述 | .High-Level Power Analysis and Optimization. presents acomprehensive description of power analysis and optimizationtechniques at the higher (architecture and behavior) levels of thedesign hierarchy, which are often the levels that yield the most powersavings. This book describes power estimation and optimizationtechniques for use during high-level (behavioral synthesis), as wellas for designs expressed at the register-transfer or architecturelevel. ..High-Level Power Analysis and Optimization. surveys thestate-of-the-art research on the following topics: powerestimation/macromodeling techniques for architecture-level designs,high-level power management techniques, and high-level synthesisoptimizations for low power. ..High-Level Power Analysis and Optimization. will be very usefulreading for students, researchers, designers, design methodologydevelopers, and EDA tool developers who are interested in low-powerVLSI design or high-level design methodologies. | | 出版日期 | Book 1998 | | 關鍵詞 | VLSI; architecture; modeling; optimization; power management; tables | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-5433-2 | | isbn_softcover | 978-1-4613-7481-7 | | isbn_ebook | 978-1-4615-5433-2 | | copyright | Springer Science+Business Media New York 1998 |
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