| 書目名稱 | Hierarchical Scheduling in Parallel and Cluster Systems | | 編輯 | Sivarama Dandamudi | | 視頻video | http://file.papertrans.cn/427/426149/426149.mp4 | | 叢書名稱 | Series in Computer Science | | 圖書封面 |  | | 描述 | Multiple processor systems are an important class of parallel systems. Over the years, several architectures have been proposed to build such systems to satisfy the requirements of high performance computing. These architectures span a wide variety of system types. At the low end of the spectrum, we can build a small, shared-memory parallel system with tens of processors. These systems typically use a bus to interconnect the processors and memory. Such systems, for example, are becoming commonplace in high-performance graph- ics workstations. These systems are called uniform memory access (UMA) multiprocessors because they provide uniform access of memory to all pro- cessors. These systems provide a single address space, which is preferred by programmers. This architecture, however, cannot be extended even to medium systems with hundreds of processors due to bus bandwidth limitations. To scale systems to medium range i. e. , to hundreds of processors, non-bus interconnection networks have been proposed. These systems, for example, use a multistage dynamic interconnection network. Such systems also provide global, shared memory like the UMA systems. However, they introduce local and | | 出版日期 | Book 2003 | | 關(guān)鍵詞 | Scala; architecture; organization; processor; scheduling | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-0133-6 | | isbn_softcover | 978-1-4613-4938-9 | | isbn_ebook | 978-1-4615-0133-6Series ISSN 1567-7974 | | issn_series | 1567-7974 | | copyright | Kluwer Academic/Plenum Publishers, New York 2003 |
The information of publication is updating
|
|
|Archiver|手機(jī)版|小黑屋|
派博傳思國際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-12 05:36
發(fā)表于 2025-3-21 18:46:08
