Titlebook: Hierarchical Modeling for VLSI Circuit Testing; Debashis Bhattacharya,John P. Hayes Book 1990 Kluwer Academic Publishers 1990 Multiplexer.

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0893-3405 atic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level comp978-1-4612-8819-0978-1-4613-1527-8Series ISSN 0893-3405

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Hierarchical Test Generation,e as SSL faults, implying that the hierarchical test generation technique allows us to obtain complete SSL fault coverage while generating tests for total bus faults only. Experimental results for sample circuits are presented, which show that this approach results in complete test sets for SSL faul

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Design for Testability,s the construction of high-level models for the unmodified circuits difficult, and complicates test generation. In this chapter, we consider redesigning circuits of this sort to enhance their regularity, and make them better suited to test generation using hierarchical approaches.

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Book 1990to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components i

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0893-3405 ributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive co

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Introduction,he last two decades, circuit design and device fabrication processes have advanced rapidly, resulting in very large-scale integrated (VLSI) circuits containing thousands or millions of transistors. The large number of components in VLSI circuits has greatly increased the importance and difficulty of testing such circuits.

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Circuit and Fault Modeling,evel circuit and fault modeling techniques are then presented. The chapter concludes with a detailed study of model construction at different abstraction levels for the special case of .-regular circuits. This illustrates the advantages of our approach over conventional modeling techniques.

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