| 書目名稱 | Hierarchical Annotated Action Diagrams | | 副標題 | An Interface-Oriente | | 編輯 | E. Cerny,B. Berkane,K. Khordoc | | 視頻video | http://file.papertrans.cn/427/426123/426123.mp4 | | 圖書封面 |  | | 描述 | Standardization of hardware description languages and theavailability of synthesis tools has brought about a remarkableincrease in the productivity of hardware designers. Yet designverification methods and tools lag behind and have difficulty indealing with the increasing design complexity. This may get worsebecause more complex systems are now constructed by (re)usingIntellectual Property blocks developed by third parties. To verifysuch designs, abstract models of the blocks and the system must bedeveloped, with separate concerns, such as interface communication,functionality, and timing, that can be verified in an almostindependent fashion. Standard Hardware Description Languages such asVHDL and Verilog are inspired by procedural `imperative‘ programminglanguages in which function and timing are inherently intertwined inthe statements of the language. Furthermore, they are not conceived tostate the intent of the design in a simple declarative way thatcontains provisions for design choices, for stating assumptions on theenvironment, and for indicating uncertainty in system timing. ..Hierarchical Annotated Action Diagrams: An Interface-Oriented..Specification and Verification Metho | | 出版日期 | Book 1998 | | 關鍵詞 | Hardware; Hardwarebeschreibungssprache; Interface; VHDL; Verilog; communication; complex system; complex sy | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-5615-2 | | isbn_softcover | 978-1-4613-7569-2 | | isbn_ebook | 978-1-4615-5615-2 | | copyright | Springer Science+Business Media New York 1998 |
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