Titlebook: Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms; A Cross-layer Approa William Fornaciari,Dimi

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The HARPA Approach to Ensure Dependable Performance,ng heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dep

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Trends in Processor Architecture main driving forces behind it, and then it focuses on a description of the main architectural features of current processors. Finally, it presents a discussion on some promising directions for future evolution of processor architectures.

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Event-Based Thermal Control for High Power Density Microprocessorsh the same topic at the HARPA-OS level. A brief analysis of the thermal control problem is presented, evidencing as the main requirement the need for thermal control at the millisecond timescale, caused by software variability in the use of CPU functional resources and fast thermal dynamics inside t

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HARPA RTre resources, enabling extremely fast adaptation to system behavior in the scale of some milliseconds, which is ideal for providing guarantees for hard-deadline applications and complements the comparatively slower responsiveness of the HARPA-OS. The HARPA-RT, exploiting a PID controller that achiev

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Improving Robustness of a Real-Time Spectrum Sensing Application with the HARPA Run-Time Engineer architectures typically enhance their designs with reliability, availability, and serviceability (RAS) schemes to correct such errors, frequently at the cost of extra clock cycles. This, in turn, leads to processor performance variability, which is undesirable for embedded consumer applications w

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Evaluating System-Level Monitors and Knobs on Real Hardwareific application while satisfying the application’s requirements and not violating any system constraints. This methodology relies on a heuristic correlation analysis between requirements, monitors, and knobs to determine the minimum subset of monitors to observe and knobs to explore to determine th

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Monitor and Knob Techniques in Network-on-Chip Architectures micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the . architecture is a fine-grained power-gating methodology targeting individual router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the

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