| 書(shū)目名稱(chēng) | Hardware Architectures for Post-Quantum Digital Signature Schemes | | 編輯 | Deepraj Soni,Kanad Basu,Ramesh Karri | | 視頻video | http://file.papertrans.cn/425/424180/424180.mp4 | | 概述 | Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based | | 圖書(shū)封面 |  | | 描述 | .This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification.? The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs..Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;.Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;.Enables designers to build hardware implementations that are resilient to a variety of side-channels.. | | 出版日期 | Book 2021 | | 關(guān)鍵詞 | Hardware Security and Trust; security-aware computer-aided design; hardware cybersecurity; hardware sig | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-030-57682-0 | | isbn_softcover | 978-3-030-57684-4 | | isbn_ebook | 978-3-030-57682-0 | | copyright | Springer Nature Switzerland AG 2021 |
The information of publication is updating
|
|
|Archiver|手機(jī)版|小黑屋|
派博傳思國(guó)際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-12 22:07
發(fā)表于 2025-3-21 17:14:01
