| 書目名稱 | Full-Chip Nanometer Routing Techniques | | 編輯 | Tsung-Yi Ho,Yao-Wen Chang,Sao-Jie Chen | | 視頻video | http://file.papertrans.cn/350/349497/349497.mp4 | | 概述 | Describes a full-chip nanometer routing techniques.A detailed description on the modern VLSI routing problems.Multilevel optimization on routing design to solve the chip complexity problem | | 叢書名稱 | Analog Circuits and Signal Processing | | 圖書封面 |  | | 描述 | .At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture...In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and t | | 出版日期 | Book 2007 | | 關(guān)鍵詞 | Design for manufacturing; Multilevel optimization; Signal integrity; VLSI; VLSI physical design; VLSI rou | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4020-6195-0 | | isbn_softcover | 978-90-481-7562-8 | | isbn_ebook | 978-1-4020-6195-0Series ISSN 1872-082X Series E-ISSN 2197-1854 | | issn_series | 1872-082X | | copyright | Springer Science+Business Media B.V. 2007 |
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