| 書目名稱 | Formal Verification of Circuits | | 編輯 | Rolf Drechsler | | 視頻video | http://file.papertrans.cn/346/345953/345953.mp4 | | 圖書封面 |  | | 描述 | Formal verification has become one of the most important stepsin circuit design. Since circuits can contain several milliontransistors, verification of such large designs becomes more and moredifficult. Pure simulation cannot guarantee the correct behavior andexhaustive simulation is often impossible. However, many designs, likeALUs, have very regular structures that can be easily described at ahigher level of abstraction. For example, describing (and verifying)an integer multiplier at the bit-level is very difficult, while theverification becomes easy when the outputs are grouped to build abit-string. Recently, several approaches for formal circuitverification have been proposed that make use of these regularities.These approaches are based on Word-Level Decision Diagrams (WLDDs)which are graph-based representations of functions (similar to BDDs)that allow for the representation of functions with a Boolean rangeand an integer domain. ..Formal Verification of Circuits. is devoted to the discussion ofrecent developments in the field of decision diagram-based formalverification. Firstly, different types of decision diagrams (includingWLDDs) are introduced and theoretical properties a | | 出版日期 | Book 2000 | | 關鍵詞 | Hardware; Hardwarebeschreibungssprache; circuit design; computer-aided design (CAD); formal verification | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4757-3184-2 | | isbn_softcover | 978-1-4419-4985-1 | | isbn_ebook | 978-1-4757-3184-2 | | copyright | Springer Science+Business Media Dordrecht 2000 |
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