| 書目名稱 | Flip-Flop Design in Nanometer CMOS |
| 副標題 | From High Speed to L |
| 編輯 | Massimo Alioto,Elio Consoli,Gaetano Palumbo |
| 視頻video | http://file.papertrans.cn/345/344341/344341.mp4 |
| 概述 | Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems.Offers in-depth analysis of the impact of nanometer effects on design tradeoffs.Pre |
| 圖書封面 |  |
| 描述 | .This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI |
| 出版日期 | Book 2015 |
| 關鍵詞 | Clocking in VLSI; Digital System Clocking; Flip-Flop Design; Flip-Flop/Latch Design; Layout Parasitics i |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-3-319-01997-0 |
| isbn_softcover | 978-3-319-34592-5 |
| isbn_ebook | 978-3-319-01997-0 |
| copyright | Springer International Publishing Switzerland 2015 |
|Archiver|手機版|小黑屋|
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