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Titlebook: Finite State Machine Datapath Design, Optimization, and Implementation; Justin Davis,Robert Reese Book 2008 Springer Nature Switzerland AG

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書目名稱Finite State Machine Datapath Design, Optimization, and Implementation
編輯Justin Davis,Robert Reese
視頻videohttp://file.papertrans.cn/344/343653/343653.mp4
叢書名稱Synthesis Lectures on Digital Circuits & Systems
圖書封面Titlebook: Finite State Machine Datapath Design, Optimization, and Implementation;  Justin Davis,Robert Reese Book 2008 Springer Nature Switzerland AG
描述Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis usin
出版日期Book 2008
版次1
doihttps://doi.org/10.1007/978-3-031-79776-7
isbn_softcover978-3-031-79775-0
isbn_ebook978-3-031-79776-7Series ISSN 1932-3166 Series E-ISSN 1932-3174
issn_series 1932-3166
copyrightSpringer Nature Switzerland AG 2008
The information of publication is updating

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