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Titlebook: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing; Hardware Architectur Sudeep Pasricha,Muhammad Shafique Book 2024 The

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發(fā)表于 2025-3-21 19:57:42 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing
副標(biāo)題Hardware Architectur
編輯Sudeep Pasricha,Muhammad Shafique
視頻videohttp://file.papertrans.cn/308/307903/307903.mp4
概述Discusses efficient implementation of machine learning in embedded, CPS, IoT, and edge computing.Offers comprehensive coverage of hardware design, software design, and hardware/software co-design and
圖書(shū)封面Titlebook: Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing; Hardware Architectur Sudeep Pasricha,Muhammad Shafique Book 2024 The
描述.This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits..
出版日期Book 2024
關(guān)鍵詞Machine learning embedded systems; Machine learning IoT; Machine learning edge computing; Smart Cyber-P
版次1
doihttps://doi.org/10.1007/978-3-031-19568-6
isbn_softcover978-3-031-19570-9
isbn_ebook978-3-031-19568-6
copyrightThe Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerl
The information of publication is updating

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發(fā)表于 2025-3-21 21:21:06 | 只看該作者
https://doi.org/10.1007/978-3-662-68073-5 neural networks can be accelerated in an energy-efficient manner. In particular, we focus on design considerations and trade-offs for mapping CNNs, Transformers, and GNNs on AI accelerators that attempt to maximize compute efficiency and minimize energy consumption by reducing the number of access to memory through efficient data reuse.
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https://doi.org/10.1007/978-3-8349-9996-2are. Thereafter, we discuss different interconnect techniques for IMC architectures proposed in the literature. Finally, different performance evaluation techniques for IMC architectures are described. We conclude the chapter with a summary and future avenues for IMC architectures for ML acceleration.
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Low- and Mixed-Precision Inference Acceleratorsd, all aiming at enabling neural network inference at the edge. In this chapter, design choices and their implications on the flexibility and energy efficiency of several accelerators supporting extremely quantized networks are reviewed.
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In-Memory Computing for AI Accelerators: Challenges and Solutionsare. Thereafter, we discuss different interconnect techniques for IMC architectures proposed in the literature. Finally, different performance evaluation techniques for IMC architectures are described. We conclude the chapter with a summary and future avenues for IMC architectures for ML acceleration.
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Embedded Machine Learning for Cyber-Physical, IoT, and Edge ComputingHardware Architectur
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