| 書目名稱 | Direct Transistor-Level Layout for Digital Blocks | | 編輯 | Prakash Gopalakrishnan,Rob A. Rutenbar | | 視頻video | http://file.papertrans.cn/281/280631/280631.mp4 | | 圖書封面 |  | | 描述 | Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. .Direct Transistor-Level Layout For Digital Blocks. proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. .The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale | | 出版日期 | Book 2004 | | 關(guān)鍵詞 | Computer-Aided Design (CAD); Layout; Transistor; algorithms; circuit design; logic; optimization | | 版次 | 1 | | doi | https://doi.org/10.1007/b117054 | | isbn_softcover | 978-1-4757-7951-6 | | isbn_ebook | 978-1-4020-8063-0 | | copyright | Springer Science+Business Media New York 2004 |
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