| 書目名稱 | Digital VLSI Design with Verilog | | 副標(biāo)題 | A Textbook from Sili | | 編輯 | John Michael Williams | | 視頻video | http://file.papertrans.cn/280/279875/279875.mp4 | | 概述 | Covers the entire Verilog language – using most of it in practice.Provides 27 lab exercises, with complete and tested answers.Explains and emphasizes synthesizability, wherever it pertains to language | | 圖書封面 |  | | 描述 | This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.?The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS. | | 出版日期 | Book 2014Latest edition | | 關(guān)鍵詞 | Digital Design and Modeling with Verilog; System Verilog; VLSI Integrated Circuit Design; Verilog Hardw | | 版次 | 2 | | doi | https://doi.org/10.1007/978-3-319-04789-8 | | isbn_softcover | 978-3-319-33098-3 | | isbn_ebook | 978-3-319-04789-8 | | copyright | Springer International Publishing Switzerland 2014 |
The information of publication is updating
|
|
|Archiver|手機(jī)版|小黑屋|
派博傳思國際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-16 13:28
發(fā)表于 2025-3-21 19:51:44
