| 書目名稱 | Digit-Serial Computation | | 編輯 | Richard Hartley,Keshab K. Parhi | | 視頻video | http://file.papertrans.cn/280/279093/279093.mp4 | | 叢書名稱 | The Springer International Series in Engineering and Computer Science | | 圖書封面 |  | | 描述 | Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real- time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit- serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the w | | 出版日期 | Book 1995 | | 關鍵詞 | Hardware; Signal; algorithm; circuit; digital signal processing; digital signal processor; radar; radio; sig | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-2327-7 | | isbn_softcover | 978-1-4613-5985-2 | | isbn_ebook | 978-1-4615-2327-7Series ISSN 0893-3405 | | issn_series | 0893-3405 | | copyright | Springer Science+Business Media New York 1995 |
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