Titlebook: Designing Embedded Processors; A Low Power Perspect J?rg Henkel,Sri Parameswaran Book 2007 Springer Science+Business Media B.V. 2007 Embedd

反抗者

S. Tano,T. Arnould,Y. Kato,T. Miyoshiensuring sufficient processing cycles are available for all tasks to meet their deadlines, even under worst-case computation requirements. However, invocations of real-time tasks typically use less than their specified worst-case computation requirements, presenting an opportunity for further energy

觀點(diǎn)

Laura Caponetti,Giovanna Castellanoesent an energy optimization approach for time constrained applications implemented on multiprocessor systems. We start by introducing a genetic algorithm that performs the mapping and scheduling of the application on the target hardware architecture. Then, we discuss in detail several voltage selec

Clinch

招募

https://doi.org/10.1007/978-1-4615-4068-7mic voltage and frequency scaling (DVFS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance loss, and has been implemented as a source-to-source level compiler transformation using the SUIF2 compiler infrastructure. Physical measurements on a noteb

陰險

https://doi.org/10.1007/978-1-4615-4068-7rprocessor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows

盟軍

Test-Cost-Sensitive Quick Reductzing the microprocessor architecture to minimize number of cycles. This chapter introduces a new generation of processors, called No-Instruction-Set- Computer (NISC), that gives the full control of the datapath to the compiler, in order to simplify the controller hardware, and enable fast architecture customizations.

AROMA

Fundamentals of Power-Aware Schedulingl principles are applicable to all such systems. This chapter provides an overview of the basics in power and performance tradeoff and in real-time system scheduling. It also discusses the benefit of power-aware scheduling via a simple example. A categorization of different power-aware scheduling techniques are presented at the end.

錫箔紙

Static DVFS SchedulingThe first technique targets a popular dynamic-priority task scheduling algorithm, i.e., the Earliest Deadline First algorithm, while the second is applicable to any fixedpriority task scheduling algorithm. Other related work is reviewed at the end of the chapter.

大酒杯

Voltage Selection for Time-Constrained Multiprocessor Systemsithm that performs the mapping and scheduling of the application on the target hardware architecture. Then, we discuss in detail several voltage selection algorithms, explicitly taking into account the transition overheads implied by changing voltage levels.

譏笑