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Titlebook: Designing Asynchronous Circuits using NULL Convention Logic (NCL); Scott C. Smith,Jia Di Book 2009 Springer Nature Switzerland AG 2009

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發(fā)表于 2025-3-21 19:21:44 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書(shū)目名稱Designing Asynchronous Circuits using NULL Convention Logic (NCL)
編輯Scott C. Smith,Jia Di
視頻videohttp://file.papertrans.cn/269/268902/268902.mp4
叢書(shū)名稱Synthesis Lectures on Digital Circuits & Systems
圖書(shū)封面Titlebook: Designing Asynchronous Circuits using NULL Convention Logic (NCL);  Scott C. Smith,Jia Di Book 2009 Springer Nature Switzerland AG 2009
描述Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differencesbetween asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Ov
出版日期Book 2009
版次1
doihttps://doi.org/10.1007/978-3-031-79800-9
isbn_softcover978-3-031-79799-6
isbn_ebook978-3-031-79800-9Series ISSN 1932-3166 Series E-ISSN 1932-3174
issn_series 1932-3166
copyrightSpringer Nature Switzerland AG 2009
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Neurophysiologische Grundlagen der Bewegunger of subtractions + 2) for the general case when . ≠ . (i.e., .0 → .1 + .1 → .1 for each subtraction +.1 → .0, loading a data on the .0 → .1 transition). Additionally, overall TPC is calculated as the worse-case TPC for any operation (e.g., for the original GCD circuit, the worse case operation is
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Introduction to Asynchronous Logic,mpared to their synchronous counterparts, without degrading performance. Furthermore, . asynchronous paradigms have a number of additional advantages, especially when designing complex circuits, like Systems-on-a-Chip (SoCs), including substantially reduced crosstalk between analog and digital circu
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Comprehensive NCL Design Example,er of subtractions + 2) for the general case when . ≠ . (i.e., .0 → .1 + .1 → .1 for each subtraction +.1 → .0, loading a data on the .0 → .1 transition). Additionally, overall TPC is calculated as the worse-case TPC for any operation (e.g., for the original GCD circuit, the worse case operation is
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Designing Asynchronous Circuits using NULL Convention Logic (NCL)
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Book 2009arnaugh maps. After studying this book, readers should have a good understanding of the differencesbetween asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Ov
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Combinational NCL Circuit Design,NCL circuit design is similar to synchronous Boolean design, where minimized equations are generated and then mapped to a set of gates; however, NCL circuits must be both input-complete and observable in order to achieve delay-insensitivity.
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