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Titlebook: Design, Analysis and Test of Logic Circuits Under Uncertainty; Smita Krishnaswamy,Igor L. Markov,John P. Hayes Book 2013 Springer Science+

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發(fā)表于 2025-3-21 16:58:52 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱Design, Analysis and Test of Logic Circuits Under Uncertainty
編輯Smita Krishnaswamy,Igor L. Markov,John P. Hayes
視頻videohttp://file.papertrans.cn/269/268801/268801.mp4
概述Presents a comprehensive overview of Logic Circuits.Combines theory with practical examples.Multi-discipline approach to the "hot" topic of uncertainty.Includes supplementary material:
叢書名稱Lecture Notes in Electrical Engineering
圖書封面Titlebook: Design, Analysis and Test of Logic Circuits Under Uncertainty;  Smita Krishnaswamy,Igor L. Markov,John P. Hayes Book 2013 Springer Science+
描述Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.
出版日期Book 2013
關(guān)鍵詞Fault-tolerance; Probabilistic logic; Reliability; Soft errors; Uncertainty
版次1
doihttps://doi.org/10.1007/978-90-481-9644-9
isbn_softcover978-94-007-9798-7
isbn_ebook978-90-481-9644-9Series ISSN 1876-1100 Series E-ISSN 1876-1119
issn_series 1876-1100
copyrightSpringer Science+Business Media Dordrecht 2013
The information of publication is updating

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Computing with Probabilistic Transfer Matrices,for PTM operations that can operate directly on the compressed forms and compute circuit error probabilities. We also develop methods to handle non-square matrices, which have not been represented as decision diagrams in the prior literature.We present several heuristic methods for further improving
地板
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Signature-Based Reliability Analysis,acy. To address this challenge, we present AnSER, our linear-time method for logic-level soft-error analysis. AnSER achieves its low runtimes by means of functional simulation signatures, which enable a fast and accurate method for computing signal probability and observability, even in the presence
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發(fā)表于 2025-3-22 15:54:47 | 只看該作者
Design for Robustness,f the interplay between signal probability, observability, and masking mechanisms. The first technique, called SiDeR, involves finding logical implications between signals, using logic simulation signatures to reduce SER. In our second technique, several alternate non-redundant realizations of the s
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發(fā)表于 2025-3-23 00:43:32 | 只看該作者
Fast and Slow Enigmas and Parental GuidanceThis chapter summarizes the research presented in the preceding chapters and suggests some possible ways in which it might be extended further for new applications, such as the analysis of process variations in logic circuits, and the analysis of biological networks.
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發(fā)表于 2025-3-23 03:42:06 | 只看該作者
Summary and Extensions,This chapter summarizes the research presented in the preceding chapters and suggests some possible ways in which it might be extended further for new applications, such as the analysis of process variations in logic circuits, and the analysis of biological networks.
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