Titlebook: Dependable Computing - EDCC-2; Second European Depe Andrzej Hlawiczka,Jo?o Gabriel Silva,Luca Simoncin Conference proceedings 1996 Springer

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書目名稱Dependable Computing - EDCC-2影響因子(影響力)




書目名稱Dependable Computing - EDCC-2影響因子(影響力)學(xué)科排名




書目名稱Dependable Computing - EDCC-2網(wǎng)絡(luò)公開度




書目名稱Dependable Computing - EDCC-2網(wǎng)絡(luò)公開度學(xué)科排名




書目名稱Dependable Computing - EDCC-2被引頻次




書目名稱Dependable Computing - EDCC-2被引頻次學(xué)科排名




書目名稱Dependable Computing - EDCC-2年度引用




書目名稱Dependable Computing - EDCC-2年度引用學(xué)科排名




書目名稱Dependable Computing - EDCC-2讀者反饋




書目名稱Dependable Computing - EDCC-2讀者反饋學(xué)科排名

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Fault injection evaluation of assigned signatures in a RISC processor,djustable) execution time and memory overhead. We have measured those overheads in a PowerPC processor and in a Transputer T805 processor, showing that they are completely adjustable. One interesting conclusion is that the best error coverage of the technique does not correspond to the highest amoun

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Design of dependable hardware: What BIST is most efficient?,s (ALU, two-port RAM, registers, latches, random logic, multiplexer-based shifters). The design characteristics and the results of simulation experiments carried out for this circuit show that the proposed solution offers high quality testing at acceptable BIST implementation costs.

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