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Titlebook: Delay Fault Testing for VLSI Circuits; Angela Krsti?,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute

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發(fā)表于 2025-3-21 17:17:47 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱Delay Fault Testing for VLSI Circuits
編輯Angela Krsti?,Kwang-Ting Cheng
視頻videohttp://file.papertrans.cn/265/264936/264936.mp4
叢書名稱Frontiers in Electronic Testing
圖書封面Titlebook: Delay Fault Testing for VLSI Circuits;  Angela Krsti?,Kwang-Ting Cheng Book 1998 Springer Science+Business Media New York 1998 VLSI.compute
描述In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader‘s understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In
出版日期Book 1998
關(guān)鍵詞VLSI; computer-aided design (CAD); design; integrated circuit; modeling; quality; simulation; stability
版次1
doihttps://doi.org/10.1007/978-1-4615-5597-1
isbn_softcover978-1-4613-7561-6
isbn_ebook978-1-4615-5597-1Series ISSN 0929-1296
issn_series 0929-1296
copyrightSpringer Science+Business Media New York 1998
The information of publication is updating

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沙發(fā)
發(fā)表于 2025-3-21 21:05:55 | 只看該作者
Path Delay Fault Classification, a test exists. Given various path sensitization criteria, paths are generally classified into several classes: single-path sensitizable, robust, non-robust, functional sensitizable and functional unsensitizable.
板凳
發(fā)表于 2025-3-22 03:27:03 | 只看該作者
地板
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5#
發(fā)表于 2025-3-22 12:11:11 | 只看該作者
Conclusions and Future Work,“noise faults” such as: distributed delay defects, power bus noise, ground bounce, substrate noise and crosstalk. Analysis shows that excessive noise most of the time leads to delay faults [19]. For example, studies have shown that the increased coupling effects produce interference between signals
6#
發(fā)表于 2025-3-22 16:06:57 | 只看該作者
Die Bedeutung der gest?rten Nasenatmung a test exists. Given various path sensitization criteria, paths are generally classified into several classes: single-path sensitizable, robust, non-robust, functional sensitizable and functional unsensitizable.
7#
發(fā)表于 2025-3-22 19:07:07 | 只看該作者
https://doi.org/10.1007/978-3-7091-9947-3ent holds for the functional sensitizable tests. The higher quality non-robust and functional sensitizable tests can be found by including the timing information into the test generation process. This chapter presents test generation algorithms that can produce high quality tests based on using the
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9#
發(fā)表于 2025-3-23 04:41:09 | 只看該作者
Allgemeine Methodik der F?zesuntersuchung“noise faults” such as: distributed delay defects, power bus noise, ground bounce, substrate noise and crosstalk. Analysis shows that excessive noise most of the time leads to delay faults [19]. For example, studies have shown that the increased coupling effects produce interference between signals
10#
發(fā)表于 2025-3-23 08:08:18 | 只看該作者
Book 1998ddition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader‘s understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In
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