Titlebook: Configurable Intelligent Optimization Algorithm; Design and Practice Fei Tao,Lin Zhang,Yuanjun Laili Book 2015 Springer International Publ

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Improvement and Hybridization of Intelligent Optimization AlgorithmAlgorithm improvement and hybridization are two important branches in the development of intelligent optimization algorithm.

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Introduction

Computing Resource Allocation with PEADGAIn this chapter, for solving optimal allocation of computing resources (OACR) problem in cloud manufacturing (CMfg) [.], serial three-layer operation configuration and parallel configuration are both applied.

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Future Trends and ChallengesIn this chapter, we give some future trends and challenges of dynamic configuration not only for intelligent optimization algorithm, but also for other algorithms used in the whole life cycle of manufacturing.

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Dynamic Representations of Complex Numberscomputer to clusters, various parallel architectures are developed for computing acceleration. In terms of the long time iteration and population based mechanism of intelligent optimization algorithm, parallelization is attainable and imperative in many complex optimization.

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https://doi.org/10.1007/978-1-4614-3489-4P) in a virtual enterprise [.] is introduced. Based on ordinary initialization, an improved binary heap strategy is configured before it with uniform population input and output to realize initialization improvement. It is designed to simplify the directed acrylic graph that represents the precedenc

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https://doi.org/10.1007/978-1-4471-4996-5omputing Resources (DS-CSCR) [.]. For addressing large-scale DS-CSCR problem, Ranking Chaos Optimization (RCO) is configured. With the consideration of large-scale irregular solution spaces, new adaptive chaos operator is designed to traverse wider spaces within a short time. Besides, dynamic heuris

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https://doi.org/10.1007/978-93-86279-30-9 shop scheduling problem (JSSP). Firstly, a permutation-based encoding scheme is presented, which can make the solution always feasible in iteration. After that, simulated annealing operator, mutation operator and a new reverse order operator are implemented on FPGA and configured for updating solut