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Titlebook: Computing with Memory for Energy-Efficient Robust Systems; Somnath Paul,Swarup Bhunia Book 2014 Springer Science+Business Media New York 2

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書(shū)目名稱Computing with Memory for Energy-Efficient Robust Systems
編輯Somnath Paul,Swarup Bhunia
視頻videohttp://file.papertrans.cn/235/234827/234827.mp4
概述Introduces new paradigm for hardware reconfigurable frameworks, which leverages dense memory array as a malleable resource, which can be used for information storage as well as computation.Merges spat
圖書(shū)封面Titlebook: Computing with Memory for Energy-Efficient Robust Systems;  Somnath Paul,Swarup Bhunia Book 2014 Springer Science+Business Media New York 2
描述This book analyzes energy and reliability as major challenges faced by designers of computing frameworks in the nanometer technology regime.? The authors describe the existing solutions to address these challenges and then reveal a new reconfigurable computing platform, which leverages high-density nanoscale memory for both data storage and computation to maximize the energy-efficiency and reliability. The energy and reliability benefits of this new paradigm are illustrated and the design challenges are discussed. Various hardware and software aspects of this exciting computing paradigm are described, particularly with respect to hardware-software co-designed frameworks, where the hardware unit can be reconfigured to mimic diverse application behavior.? Finally, the energy-efficiency of the paradigm described is compared with other, well-known reconfigurable computing platforms.
出版日期Book 2014
關(guān)鍵詞Energy-efficient Computing; Energy-efficient FPGA; Energy-efficient GPU; Energy-efficient Reconfigurabl
版次1
doihttps://doi.org/10.1007/978-1-4614-7798-3
isbn_softcover978-1-4939-4819-2
isbn_ebook978-1-4614-7798-3
copyrightSpringer Science+Business Media New York 2014
The information of publication is updating

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Delay Insertion and Clock Skew Scheduling,sing units and FPGAs. Motivated by the fact that hardware reconfigurable frameworks like FPGAs can significantly benefit energy-efficiency for compute-intensive workloads, we then discuss some well-known hardware reconfigurable architectures. Finally we discuss the scaling challenges for fully-spati
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Timing Properties of Synchronous Systems,ntional hardware and software reconfigurable frameworks at nanoscale technologies. We then provide an outline for a new computing model which bridges the gap between memory and logic. Given the rapid evolution of CMOS and non-CMOS memory technologies, we explain the benefits of such in-memory comput
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https://doi.org/10.1007/978-0-387-71056-3RAM, DRAM etc.) or permanently (for example by non-volatile memories such as Flash, magnetic disks etc.). In this chapter we first draw the outline how the embedded memory may be used for computing as well in a time-multiplexed hardware reconfigurable system. In particular, this chapter makes the fo
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