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Titlebook: Computer Engineering and Technology; 20th CCF Conference, Weixia Xu,Liquan Xiao,Zhenzhen Zhu Conference proceedings 2016 Springer Nature Si

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21#
發(fā)表于 2025-3-25 04:45:29 | 只看該作者
An AWGR-Based High Performance Optical Interconnect Architecture for Exascale Systemsizing exascale computing is the fundamental challenge of communication networks. We propose a high performance optical interconnect architecture based on Arrayed waveguide grating router (AWGR) with WDM wavelength routing, the inherent parallelism in AWGRs and multi-hop switching provide high scalab
22#
發(fā)表于 2025-3-25 07:44:11 | 只看該作者
Accelerating Nystr?m Kernel Independent Component Analysis with Many Integrated Core Architecturel in many practical tasks such as speech separation due to its robustness on varying source distributions. Recently, Nystr?m-KICA (NKICA) incorporates a low-rank approximation and low-complexity sampling method to reduce the computational complexity of KICA. In this paper, we show that the computati
23#
發(fā)表于 2025-3-25 14:59:17 | 只看該作者
Conference proceedings 2016 August 2016.?.The 21 full papers presented were carefully reviewed and selected from 120 submissions. They are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon..
24#
發(fā)表于 2025-3-25 17:59:41 | 只看該作者
1865-0929 are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon..978-981-10-3158-8978-981-10-3159-5Series ISSN 1865-0929 Series E-ISSN 1865-0937
25#
發(fā)表于 2025-3-25 22:19:26 | 只看該作者
26#
發(fā)表于 2025-3-26 04:11:18 | 只看該作者
27#
發(fā)表于 2025-3-26 08:21:40 | 只看該作者
Opinions on Tax Evasion in Armeniatention time of STT-RAM to explore its different write performance, and propose a novel STT-RAM L1 cache architecture implemented with volatile STT-RAM as well as its related refresh scheme. The performance of proposed design is the same as SRAM L1 cache while its overall power consumption is only 63.8% of the latter one.
28#
發(fā)表于 2025-3-26 12:07:23 | 只看該作者
Robert W. McGee,Marcelo J. Rossitional single-threshold algorithm, experimental results show that dual-threshold adaptive DVFS can save more power with no obviously performance reduction. The performance of most benchmarks is beyond 90% of the original performance, while the power optimization can be up to 35%.
29#
發(fā)表于 2025-3-26 16:01:34 | 只看該作者
30#
發(fā)表于 2025-3-26 18:23:58 | 只看該作者
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