| 書目名稱 | Compilation Techniques for Reconfigurable Architectures |
| 編輯 | Jo?o M.P. Cardoso,Pedro C. Diniz |
| 視頻video | http://file.papertrans.cn/232/231235/231235.mp4 |
| 概述 | Introduces hardware compilation and reconfigurable computing architectures.Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.Bridges |
| 圖書封面 |  |
| 描述 | The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. T |
| 出版日期 | Book 2009 |
| 關(guān)鍵詞 | Compiler; Computer; Computer Architecture; FPGA; Field Programmable Gate Array; Hardware; Hardware Compila |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-0-387-09671-1 |
| isbn_softcover | 978-1-4419-3510-6 |
| isbn_ebook | 978-0-387-09671-1 |
| copyright | Springer-Verlag US 2009 |
|Archiver|手機(jī)版|小黑屋|
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