| 書目名稱 | Clock Generators for SOC Processors | | 副標(biāo)題 | Circuits and Archite | | 編輯 | Amr M. Fahim | | 視頻video | http://file.papertrans.cn/229/228343/228343.mp4 | | 概述 | Explores problems in the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors.Comprehensive coverage includes summary chapters on circuit theory as well as | | 圖書封面 |  | | 描述 | This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are | | 出版日期 | Book 2005 | | 關(guān)鍵詞 | CMOS; Fahim; Filter; digital signal processor; drift transistor; published; system on chip (SoC) | | 版次 | 1 | | doi | https://doi.org/10.1007/b117041 | | isbn_softcover | 978-1-4419-5470-1 | | isbn_ebook | 978-1-4020-8080-7 | | copyright | Springer-Verlag US 2005 |
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