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Titlebook: Biological and Artificial Intelligence Environments; Bruno Apolloni,Maria Marinaro,Roberto Tagliaferri Conference proceedings 2005 Springe

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樓主: clannish
21#
發(fā)表于 2025-3-25 06:32:17 | 只看該作者
Mining Yeast Gene Microarray Data with Latent Variable Modelsbracing the Generative Topographic Mapping as a special case. This article describes the use of PPS for the analysis of yeast gene expression levels from microarray chips showing its effectiveness for high-D data visualization and clustering.
22#
發(fā)表于 2025-3-25 08:21:52 | 只看該作者
23#
發(fā)表于 2025-3-25 12:13:18 | 只看該作者
Eine ausführliche Falldarstellung deal with different data types (real, integer, and class). Moreover, it produces human-readable rules - which is fundamental in order to make the system useful to physicians. First results showed interesting rules, suggesting that this approach is viable and deserves deeper research.
24#
發(fā)表于 2025-3-25 19:51:19 | 只看該作者
Hersendood en postmortale orgaandonatie, a large fraction of proteins of interest. Arrangements of .-sheets are predicted with special recursive neural networks architectures. We first present a unifying framework for description of a large class of contextual recursive models and then show how it is possible to solve the problem at some extent of success.
25#
發(fā)表于 2025-3-25 20:58:05 | 只看該作者
26#
發(fā)表于 2025-3-26 03:47:22 | 只看該作者
27#
發(fā)表于 2025-3-26 08:00:57 | 只看該作者
28#
發(fā)表于 2025-3-26 08:34:33 | 只看該作者
29#
發(fā)表于 2025-3-26 15:35:29 | 只看該作者
Analysis of Oligonucleotide Microarray Images Using a Fuzzy Sets Approach in HLA Typingth evaluation of spot activity, then it estimates probe hybridization levels from activity levels. The method is designed for being readily usable by the biologist, by adopting fuzzy linguistic variables which are familiar to the user and by featuring a standard and complete graphical interface.
30#
發(fā)表于 2025-3-26 18:02:03 | 只看該作者
Neural Hardware Based on Kernel Methods for Industrial and Scientific Applications case studies for which the ability of achieving real-time processing is of paramount importance. The performance of such architectures is then analyzed in terms of its speed of execution, occupancy of the hardware modules available in a Virtex II FPGA chip, and classification error.
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