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Titlebook: Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Co; Frank Ohnh?user Book 2015 Springer-V

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樓主: 多愁善感
21#
發(fā)表于 2025-3-25 06:11:22 | 只看該作者
External Driver Circuitry and Test of ADCs,ation (see Chap. .), if the external connections are adequate [.]. Whenever the ADCs performance is pushed into new dimensions, then the external driver circuitry needs to be reconsidered. The analog inputs and the reference inputs are most critical, because a fast and accurate settling is required
22#
發(fā)表于 2025-3-25 09:05:34 | 只看該作者
Digital-to-Analog Converters,. Chapter . discusses the test and verification of ADCs as well as the external circuitry around the ADC in an application. This chapter will now complement the topic of data converters with an introduction of digital-to-analog converters (DACs). In industrial applications, they are often used as th
23#
發(fā)表于 2025-3-25 14:10:58 | 只看該作者
e the problem of achieving high performance and resolution with the lowest possible power dissipation, while the digital circuitry generates distortion in supply, ground and substrate. This book explains the co978-3-662-51412-2978-3-662-47020-6
24#
發(fā)表于 2025-3-25 16:57:06 | 只看該作者
Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Co
25#
發(fā)表于 2025-3-25 21:20:09 | 只看該作者
26#
發(fā)表于 2025-3-26 03:43:49 | 只看該作者
27#
發(fā)表于 2025-3-26 07:02:15 | 只看該作者
DIGE Analysis of Animal Tissuesging the clock frequency. Furthermore, the clock jitter only affects the system noise hardly. The input signal will be sampled at a wrong point of time. However, due to the oversampling, the input frequencies are low anyhow, where noise based on clock jitter can normally be neglected.
28#
發(fā)表于 2025-3-26 09:27:04 | 只看該作者
https://doi.org/10.1007/978-1-4939-7268-5e controlling element. The system performance will then fully rely on the DAC and the absolute values such as INL, offset or gain are important. If they are used inside a control loop, which will increment or decrement the DAC value, then equal step size is required, which is reflected in the DNL.
29#
發(fā)表于 2025-3-26 15:17:45 | 只看該作者
30#
發(fā)表于 2025-3-26 18:43:44 | 只看該作者
https://doi.org/10.1007/978-1-0716-2831-7 described in Sect. ..?In a next step, trim solutions for these ADCs were evaluated. A purely digital trim solution is proposed in Sect. . followed by an INL-trim method in Sect. .. A novel method to measure capacitive matching, which is required for the trim algorithm, will further reduce the production costs. It is discussed in Sect. ..
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