Titlebook: Analog and Mixed-Signal Circuits in Nanoscale CMOS; Rui Paulo da Silva Martins,Pui-In Mak Book 2023 The Editor(s) (if applicable) and The

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Martin Bohner,Stefan Siegmund,Petr Stehlíkrs. For the DC-type energy harvesting, we exploit the algebraic series-parallel (ASP) topology to reduce both the intrinsic power stage conduction and parasitic losses, while enabling high-efficiency reconfigurable voltage conversion. We demonstrated all the design approaches with silicon-validated results.

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Difference Equations with U-Nonlinearitypseudo-continuous control loop design. The second work is a dual symmetrical SC converter with dynamic power cell allocation, such that the two outputs can efficiently share the power converter cells with higher system efficiency and smaller chip area. This chapter included all design considerations.

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Ultra-Low-Voltage Clock References implemented in 28?nm CMOS. It features an asymmetric swing-boosted RC (resistor-capacitor) network and a dual-path comparator to surmount the challenges of sub-0.5?V operation while achieving temperature resilience. This chapter elaborates both designs in detail.

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Integrated Energy Harvesting Interfacesrs. For the DC-type energy harvesting, we exploit the algebraic series-parallel (ASP) topology to reduce both the intrinsic power stage conduction and parasitic losses, while enabling high-efficiency reconfigurable voltage conversion. We demonstrated all the design approaches with silicon-validated results.

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