Titlebook: Analog Design Issues in Digital VLSI Circuits and Systems; A Special Issue of A Juan J. Becerra,Eby G. Friedman Book 1997 Springer Science+

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CMOS PLL Design in a Digital Chip Environment are defined to meet the requirements of the digital chip, not the analog portions of the PLL. The environment defined by the digital requirements includes the package, the process and the dominant noise source. Packages for complex digital chips are larger and have more complex frequency and signal

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Latin Hypercube Sampling Monte Carlo Estimation of Average Quality Index for Integrated Circuitsure (AQI) or Parametric Yield estimation of MOS VLSI circuits. In this contribution a new method of . technique, viz. the . (.) method is presented which improves the efficiency of AQI estimation in integrated circuits especially for MOS digital circuits. This method is similar to the . (.) method e

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Analysis of Metastable Operation in a CMOS Dynamic D-Latchistable circuit operates at high frequencies. As far as we know, there is not any work published that justifies and formally characterizes metastable behavior in dynamic latches. With current technologies, dynamic latches are widely used in high-performance VLSI circuits, mainly due to their lower c

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